Voltage regulators which supply the digital core logic in mobile devices (for example a camera phone) often operate in a low power ‘standby’ mode. They should be able to transition ‘gracefully’ into and out of this mode without introducing undesirable transient voltage changes and a consequent loss of data.
A known type of architecture for realizing this incorporates a pair of regulators in parallel, an auxiliary (low power) PMOS output regulator which provides regulation in the low power ‘standby’ mode, and a main NMOS output regulator which handles the high load current requirement during normal operation, that is in the ‘streaming’ mode. The outputs of these two regulators are connected together. The PMOS output regulator is set to provide a slightly lower voltage than the stronger NMOS output regulator and is forced off when the latter regulator is enabled, during a transition from the ‘standby’ mode to the ‘streaming’ mode. A return to the ‘standby’ mode from the ‘streaming’ mode is completed when the NMOS output regulator is disabled and the PMOS output regulator regains control of the output.
It is highly desirable for the regulated output voltage to remain within specification at all times. This requirement poses specific design challenges during the transitions between the ‘standby’ and ‘streaming’ modes of operation. In particular, during the transition from ‘streaming’ mode to ‘standby’ mode, the auxiliary regulator should turn on quickly enough, as the main regulator turns off, to take over the regulation of the output and help prevent its voltage from falling below specification.